Page Not Found
Page not found. Your pixels are in another canvas.
A list of all the posts and pages found on the site. For you robots out there is an XML version available for digesting as well.
Page not found. Your pixels are in another canvas.
About me
This is a page not in th emain menu
Published:
Segmentation and Pose estimation on YOLOv8 demonstration at SHARPER Night 2023
Published:
Alan Turing making the Turing test on the desk
Published:
A robot thinks like in The Thinker pose of Auguste Rodin
Short description of portfolio item number 1
Short description of portfolio item number 2
Published in Ital-IA, 2022
Published in IEEE Access, 2022
The recent increasing demand of Silicon-on-Chip devices has triggered a significant impact on the industrial processes of leading semiconductor companies. The semiconductor industry is redesigning internal technology processes trying to optimize costs and production yield. To achieve this target a key role is played by the intelligent early wafer defects identification task. The Electrical Wafer Sorting (EWS) stage allows an efficient wafer defects analysis by processing the visual map associated to the wafer. The goal of this contribution is to provide an effective solution to perform automatic evaluation of the EWS defect maps. The proposed solution leverages recent approaches of deep learning both supervised and unsupervised to perform a robust EWS defect patterns classification in different device technologies including Silicon and Silicon Carbide. This method embeds an end-to-end pipeline for supervised EWS defect patterns classification including a hierarchical unsupervised system to assess novel defects in the production line. The implemented āUnsupervised Learning Blockā embeds ad-hoc designed Dimensionality Reduction combined with Clustering and a Metrics-driven Classification Sub-Systems. The proposed āSupervised Learning Blockā includes a Convolutional Neural Network trained to perform a supervised classification of the Wafer Defect Maps (WDMs). The proposed system has been evaluated on several datasets, showing effective performance in the classification of the defect patterns (average accuracy about 97%).
Recommended citation: R. E. Sarpietro et al. "Explainable Deep Learning System for Advanced Silicon and Silicon Carbide Electrical Wafer Defect Map Assessment," IEEE Access, vol. 10, pp. 99102-99128, 2022 doi: 10.1109/ACCESS.2022.3204278
Published in AEIT, 2022
Published:
This is a description of your talk, which is a markdown files that can be all markdown-ified like any other post. Yay markdown!
Published:
This is a description of your conference proceedings talk, note the different field in type. You can put anything in this field.
Undergraduate course, University 1, Department, 2014
This is a description of a teaching experience. You can use markdown like any other post.
Workshop, University 1, Department, 2015
This is a description of a teaching experience. You can use markdown like any other post.